2305

3.3V Zero Delay Low Skew Buffer

The 2305 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on IDT's proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or direct; Clock outputs from 10 to 133 MHz\nZero input-output delay\nFour low skew (<250 ps) outputs\nDevice-to-device skew <700 ps\nFull CMOS outputs with 25 mA output drive capability at TTL levels\n5 V tolerant CLKIN\nTri-state mode for board-level testing\nAdvanced, low power, sub-micron CMOS process\nOpe;

2305

Insulated Low Thermal EMF Spade Lug

2305

包裝：散裝 類別：連接器，互連器件 系列間適配器 描述：ADAPT SPADE LUG TO BAN JACK 2PC

2305

包裝：散裝 功能：電機(jī)控制器/驅(qū)動(dòng)器，觸覺/振動(dòng) 類別：開發(fā)板，套件，編程器 評(píng)估和演示板及套件 描述：BOARD HAPTIC MOTOR CTLR DRV2605L

2305

包裝：散裝 類別：RF/IF，射頻/中頻和 RFID RFI 和 EMI - 屏蔽和吸收材料 描述：RFSW,NAR,0

Laird Technologies EMI

230500

2AG Slo-Blo Fuse

AxialLeadandCartridgeFuses SubminiatureGlassBody 2AGSlo-Blo?Fuse229/230Series The2AGSlo-Blo?fusesareavailableincartridgeformorwithaxialleads.Axialleadedfusesareboardwashable.2AGfusesprovidethesameperformancecharacteristicsastheir3AGcounterpart,whileoccup

2305000

Capacitive Sensor

Features ■M18×1threadedbarrel ■Chrome-platedbrass ■Fineadjustmentviapotentiometer ■AC2-wire,20…250VAC ■NOcontact ■Cableconnection Functionalprinciple Capacitiveproximityswitchesaredesigned fornon-contactandwear-freedetection ofelectricallyconductiveaswellasnon

2305004

FLK 16/24/DV-AI/EZ-DR/400 - 電纜

圓形系統(tǒng)電纜; 控制器: Emerson Delta V; 連接 1： IDC/FLK孔式連接器 (1x 24-位置); 連接 2: IDC/FLK孔式連接器 (1x 16-位置); 電纜長(zhǎng)度: 4 m;

230500P

2AG Slo-Blo Fuse

SubminiatureGlassBody AxialLeadandCartridgeFuses 2AGSlo-Blo?Fuse229P/230PSeries The2AGSlo-Blo?fusesareavailableincartridgeformorwithaxialleads.Axialleadedfusesareboardwashable.2AGfusesprovidethesameperformancecharacteristicsastheir3AGcounterpart,whileocc

2305-1

3.3 Volt Zero Delay Low Skew Buffer

The IDT2305 is a low phase noise, high-speed PLL based, low-skew zero delay buffer. Based on the IDT proprietary low jitter Phase Locked Loop (PLL) techniques, the device provides four low skew outputs at speeds up to 133 MHz at 3.3 V. The outputs can be generated from the PLL (for zero delay), or d; Clock outputs from 10 to 133 MHz\nZero input-output delay\nFour low skew (<250 ps) outputs\nDevice-to-device skew <700 ps\nFull CMOS outputs with 25 mA output drive capability at TTL levels\n5 V tolerant CLKIN\nTri-state mode for board-level testing\nAdvanced, low power, sub-micron CMOS process\nOpe;