2308

3.3V Zero Delay Clock Multiplier

The 2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The 2; ? Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency\n? Distributes one clock input to two banks of four outputs\n? Separate output enable for each output bank\n? External feedback (FBK) pin is used to synchronize the outputs to the clock input\n? Ou;

2308

Insert Molded Coil

2308

Performance Masking Tape

2308

Nylon Hose Clamps

2308

包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：RF/IF，射頻/中頻和 RFID RF 天線 描述：RF ANT 2.4/5.4GHZ PCB TRACE CAB

230800

2AG Slo-Blo Fuse

AxialLeadandCartridgeFuses SubminiatureGlassBody 2AGSlo-Blo?Fuse229/230Series The2AGSlo-Blo?fusesareavailableincartridgeformorwithaxialleads.Axialleadedfusesareboardwashable.2AGfusesprovidethesameperformancecharacteristicsastheir3AGcounterpart,whileoccup

230800P

2AG Slo-Blo Fuse

SubminiatureGlassBody AxialLeadandCartridgeFuses 2AGSlo-Blo?Fuse229P/230PSeries The2AGSlo-Blo?fusesareavailableincartridgeformorwithaxialleads.Axialleadedfusesareboardwashable.2AGfusesprovidethesameperformancecharacteristicsastheir3AGcounterpart,whileocc

2308033-1

SOLARLOK 2.0 CONNECTOR

TEConnectivity’s(TE)SOLARLOK2.0connectorisatool-less fieldinstallableproductusingInsulationDisplacementContact (IDC)technology.Offeringtheinstalleraneasy,quickandreliable connectionfromthePVCabletothePVPanel.Thisincorporates theSOLARLOK1500VPV4-Sinterfacea

2308124

MACX MCR-S-MUX-TB - HART傳輸模塊

HART端子模塊用于應(yīng)用來(lái)自HART兼容的信號(hào)轉(zhuǎn)換器或現(xiàn)場(chǎng)設(shè)備的信號(hào)，并將它們傳送到MACX?MCR-S-MUX HART多路復(fù)用器。;

2308-1DCG

3.3V ZERO DELAY CLOCK MULTIPLIER

FEATURES: ?Phase-LockLoopClockDistributionforApplicationsranging from10MHzto133MHzoperatingfrequency ?Distributesoneclockinputtotwobanksoffouroutputs ?Separateoutputenableforeachoutputbank ?Externalfeedback(FBK)pinisusedtosynchronizetheoutputs tothecl