74ACT16825DLR集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器規(guī)格書PDF中文資料

74ACT16825DLR屬于集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器。由美國德州儀器公司制造生產(chǎn)的74ACT16825DLR緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動(dòng)器、接收器和收發(fā)器允許隔離對(duì)某個(gè)電路的邏輯信號(hào)的訪問，以用于另一電路。緩沖器將其輸入信號(hào)（不變或反相）傳遞到其輸出，并可能用于清除弱信號(hào)或驅(qū)動(dòng)負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進(jìn)行隔離通信。

Members of the Texas Instruments

WidebusE Family

Inputs Are TTL-Voltage Compatible

Provide Extra Data Width Necessary for

Wider Address/Data Paths or Buses With

Parity

Flow-Through Architecture Optimizes

PCB Layout

Distributed VCC and GND Pin Configuration

Minimizes High-Speed Switching Noise

EPICE (Enhanced-Performance Implanted

CMOS) 1-mm Process

Package Options Include Plastic 300-mil

Shrink Small-Outline (DL) Packages Using

25-mil Center-to-Center Pin Spacings and

380-mil Fine-Pitch Ceramic Flat (WD)

Packages Using 25-mil Center-to-Center

Spacings

description

The ’ACT16825 18-bit buffers/drivers are

designed specifically to improve both the

performance and density of 3-state memory

address drivers, clock drivers, and bus-oriented

receivers and transmitters.

The ’ACT16825 can be used as two 9-bit buffers

or one 18-bit buffer. They provide true data from

A to Y.

The 3-state control gate is a 2-input NOR gate;

therefore, if either output-enable (OE1 or OE2)

input is high, all nine affected outputs are in the

high-impedance state.

The 74ACT16825 is packaged in TI’s shrink small-outline package, which provides twice the I/O pin count and

functionality of standard small-outline packages in the same printed-circuit-board area.

The 54ACT16825 is characterized for operation over the full military temperature range of –55°C to 125°C. The

74ACT16825 is characterized for operation from –40°C to 85°C.