74HC138DB

3-to-8 line decoder/demultiplexer; inverting; ? Complies with JEDEC standard no. 7A\n? Input levels:? For 74HC138: CMOS level\n? For 74HCT138: TTL level\n\n? Demultiplexing capability\n? Multiple input enable for easy expansion\n? Ideal for memory chip select decoding\n? Active LOW mutually exclusive outputs\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? Multiple package options\n? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four '138 ICs and one inverter. The '138 can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

74HC138DB

3-to-8 line decoder/demultiplexer; inverting

GENERALDESCRIPTION The74HC/HCT138arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?Demultiplexingcapability ?Multipleinputenableforeasyexpansion ?Idealformemory

74HC138DB,112

Package：16-SSOP（0.209"，5.30mm 寬）；包裝：管件 類別：集成電路（IC） 信號開關(guān)，多路復(fù)用器，解碼器 描述：IC DECODER/DEMUX 1X3:8 16SSOP

Nexperia USA Inc.

74HC138DB,118

Package：16-SSOP（0.209"，5.30mm 寬）；包裝：管件 類別：集成電路（IC） 信號開關(guān)，多路復(fù)用器，解碼器 描述：IC DECODER/DEMUX 1X3:8 16SSOP

Nexperia USA Inc.

74HC138D-T

High-SpeedCMOSLogic3-to8-LineDecoder/DemultiplexerInvertingandNoninverting

74HC138N

3-to-8linedecoder/demultiplexer;inverting

GENERALDESCRIPTION The74HC/HCT138arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?Demultiplexingcapability ?Multipleinputenableforeasyexpansion ?Idealformemory

74HC138PW

3-to-8linedecoder/demultiplexer;inverting

GENERALDESCRIPTION The74HC/HCT138arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?Demultiplexingcapability ?Multipleinputenableforeasyexpansion ?Idealformemory

74HC138PW

3-to-8linedecoder/demultiplexer;inverting

1.Generaldescription The74HC138;74HCT138decodesthreebinaryweightedaddressinputs(A0,A1andA2)to eightmutuallyexclusiveoutputs(Y0toY7).Thedevicefeaturesthreeenableinputs(E1,E2and E3).EveryoutputwillbeHIGHunlessE1andE2areLOWandE3isHIGH.Thismultipleena

74HC138T

3-8decoder/demultiplexer;inverter

CD74HC138

High-SpeedCMOSLogic3-to8-LineDecoder/DemultiplexerInvertingandNoninverting