74HC174

Hex D-type flip-flop with reset; positive-edge trigger

GENERALDESCRIPTION The74HC/HCT174arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?Sixedge-triggeredD-typeflip-flops ?Asynchronousmasterreset ?Outputcap

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74HC174

Hex D-type flip-flop with reset; positive-edge trigger

1.Generaldescription The74HC174;74HCT174arehexpositiveedge-triggeredD-typeflip-flopswithindividualdata inputs(Dn)andoutputs(Qn).Thecommonclock(CP)andmasterreset(MR)inputsloadandreset allflip-flopssimultaneously.TheD-inputthatmeetstheset-upandholdtimerequ

74HC174D

Hex D-type flip-flop with reset; positive-edge trigger

GENERALDESCRIPTION The74HC/HCT174arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?Sixedge-triggeredD-typeflip-flops ?Asynchronousmasterreset ?Outputcap

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74HC174D

Hex D-type flip-flop with reset; positive-edge trigger

1.Generaldescription The74HC174;74HCT174arehexpositiveedge-triggeredD-typeflip-flopswithindividualdata inputs(Dn)andoutputs(Qn).Thecommonclock(CP)andmasterreset(MR)inputsloadandreset allflip-flopssimultaneously.TheD-inputthatmeetstheset-upandholdtimerequ

74HC174D

Hex D-type flip-flop with reset; positive-edge trigger; ? Input levels:? For 74HC174: CMOS level\n? For 74HCT174: TTL level\n\n? Six edge-triggered D-type flip-flops\n? Asynchronous master reset\n? Complies with JEDEC standard no. 7A\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V.\n\n? Multiple package options\n? Specified from -40 °C to +85 °C and -40 °C to +125 °C.\n;

The 74HC174; 74HCT174 are hex positive edge -triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR ) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

74HC174DB

Hex D-type flip-flop with reset; positive-edge trigger; ? Input levels:? For 74HC174: CMOS level\n? For 74HCT174: TTL level\n\n? Six edge-triggered D-type flip-flops\n? Asynchronous master reset\n? Complies with JEDEC standard no. 7A\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V.\n\n? Multiple package options\n? Specified from -40 °C to +85 °C and -40 °C to +125 °C.\n;

The 74HC174; 74HCT174 are hex positive edge -triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR ) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n

74HC174DB

Hex D-type flip-flop with reset; positive-edge trigger

GENERALDESCRIPTION The74HC/HCT174arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?Sixedge-triggeredD-typeflip-flops ?Asynchronousmasterreset ?Outputcap

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74HC174D-Q100

Hex D-type flip-flop with reset; positive-edge trigger

1.Generaldescription The74HC174-Q100;74HCT174-Q100arehexpositiveedge-triggeredD-typeflip-flopswith individualdatainputs(Dn)andoutputs(Qn).Thecommonclock(CP)andmasterreset(MR) inputsloadandresetallflip-flopssimultaneously.TheD-inputthatmeetstheset-upandhold

74HC174D-Q100

Hex D-type flip-flop with reset; positive-edge trigger; ? Automotive product qualification in accordance with AEC-Q100 (Grade 1)? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n? Input levels:? For 74HC174-Q100: CMOS level\n? For 74HCT174-Q100: TTL level\n\n? Six edge-triggered D-type flip-flops\n? Asynchronous master reset\n? Complies with JEDEC standard no. 7A\n? ESD protection:? MIL-STD-883, method 3015 exceeds 2000 V\n? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)\n\n? Multiple package options\n;

The 74HC174-Q100; 74HCT174-Q100 are hex positive edge-triggered D-type flip-flops with individual data inputs (Dn) and outputs (Qn). The common clock (CP) and master reset (MR) inputs load and reset all flip-flops simultaneously. The D-input that meets the set-up and hold time requirements on the LOW-to-HIGH clock transition is stored in the flip-flop and appears at the Q output. A LOW on MR causes the flip-flops and outputs to be reset LOW. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

74HC174N

Hex D-type flip-flop with reset; positive-edge trigger

GENERALDESCRIPTION The74HC/HCT174arehigh-speedSi-gateCMOSdevicesandarepincompatiblewithlowpowerSchottkyTTL(LSTTL).TheyarespecifiedincompliancewithJEDECstandardno.7A. FEATURES ?Sixedge-triggeredD-typeflip-flops ?Asynchronousmasterreset ?Outputcap

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