74LVC1G175GW

Single D-type flip-flop with reset; positive-edge trigger

Generaldescription The74LVC1G175isahigh-performance,low-voltage,Si-gateCMOSdevice,superiortomostadvancedCMOScompatibleTTLfamilies. Theinputcanbedrivenfromeither3.3Vor5Vdevices.Thisfeatureallowstheuseofthisdeviceinamixed3.3Vand5Venvironment. Th

PHI

74LVC1G175GW

Single D-type flip-flop with reset; positive-edge trigger

Generaldescription The74LVC1G175isalow-power,low-voltagesinglepositiveedgetriggeredD-typeflip-flopwithindividualdata(D)input,clock(CP)input,masterreset(MR)input,andQoutput. Themasterreset(MR)isanasynchronousactiveLOWinputandoperatesindependentlyofthe

74LVC1G175GW

絲?。?a target="_blank" title="Marking" href="/yt/marking.html">YT；Package：SOT363-2；Single D-type flip-flop with reset; positive-edge trigger

1.Generaldescription The74LVC1G175isalow-power,low-voltagesinglepositiveedgetriggeredD-typeflip-flopwith individualdata(D)input,clock(CP)input,masterreset(MR)input,andQoutput. Themasterreset(MR)isanasynchronousactiveLOWinputandoperatesindependentlyofthe

74LVC1G175GW

Single D-type flip-flop with reset; positive-edge trigger; ? Wide supply voltage range from 1.65 V to 5.5 V\n? 5 V tolerant inputs for interfacing with 5 V logic\n? High noise immunity\n? Complies with JEDEC standard:? JESD8-7 (1.65 V to 1.95 V)\n? JESD8-5 (2.3 V to 2.7 V)\n? JESD8B/JESD36 (2.7 V to 3.6 V).\n\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V.\n\n? ±24 mA output drive (VCC = 3.0 V)\n? CMOS low power consumption\n? Latch-up performance exceeds 250 mA\n? Direct interface with TTL levels\n? Inputs accept voltages up to 5 V\n? Multiple package options\n? Specified from -40 °C to +85 °C and -40 °C to +125 °C.\n;

The 74LVC1G175 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output.\n The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.\n The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment.\n This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.\n Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.\n

74LVC1G175GW-Q100

Single D-type flip-flop with reset; positive-edge trigger; ? Automotive product qualification in accordance with AEC-Q100 (Grade 1)? Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n\n? Wide supply voltage range from 1.65 V to 5.5 V\n? 5 V tolerant inputs for interfacing with 5 V logic\n? High noise immunity\n? Complies with JEDEC standard:? JESD8-7 (1.65 V to 1.95 V)\n? JESD8-5 (2.3 V to 2.7 V)\n? JESD8B/JESD36 (2.7 V to 3.6 V).\n\n? ±24 mA output drive (VCC = 3.0 V)\n? CMOS low power consumption\n? Latch-up performance exceeds 250 mA\n? Direct interface with TTL levels\n? Inputs accept voltages up to 5 V\n? ESD protection:? MIL-STD-883, method 3015 exceeds 2000 V\n? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 Ω)\n\n;

The 74LVC1G175-Q100 is a low-power, low-voltage single positive edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, master reset (MR) input, and Q output. The master reset (MR) is an asynchronous active LOW input and operates independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation. The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device in a mixed 3.3 V and 5 V environment. This device is fully specified for partial power-down applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down. Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times.\n This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.\n

74LVC1G175GW.125

Single D-type flip-flop with reset; positive-edge trigger

74LVC1G175GW-Q100

絲?。?a target="_blank" title="Marking" href="/yt/marking.html">YT；Package：SC-88；Single D-type flip-flop with reset; positive-edge trigger

74LVC1G175GW,125

Package：6-TSSOP，SC-88，SOT-363；包裝：管件 功能：復位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 1BIT 6TSSOP

Nexperia USA Inc.

74LVC1G175GW,165

Package：6-TSSOP，SC-88，SOT-363；包裝：管件 功能：復位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 1BIT 6TSSOP

Nexperia USA Inc.

74LVC1G175GW-Q100H

Package：6-TSSOP，SC-88，SOT-363；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：復位 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 1BIT 6TSSOP

Nexperia USA Inc.