74LVC1G80GS

Single D-type flip-flop; positive-edge trigger

The 74LVC1G80 provides a single positive-edge triggered D-type flip-flop.\n Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The input pin D must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable opera; ? Wide supply voltage range from 1.65 V to 5.5 V\n? High noise immunity\n? Complies with JEDEC standard:? JESD8-7 (1.65 V to 1.95 V)\n? JESD8-5 (2.3 V to 2.7 V)\n? JESD8B/JESD36 (2.7 V to 3.6 V)\n\n? ESD protection:? HBM JESD22-A114F exceeds 2000 V\n? MM JESD22-A115-A exceeds 200 V\n\n? ±24 mA outpu;

74LVC1G80GS

絲?。?a target="_blank" title="Marking" href="/vt/marking.html">VT；Package：SOT1202；Single D-type flip-flop; positive-edge trigger

1.Generaldescription The74LVC1G80isasinglepositive-edgetriggeredD-typeflip-flop.DataattheD-inputthatmeets theset-upandholdtimerequirementsontheLOW-to-HIGHclocktransitionwillbestoredinthe flip-flopanditscomplementwillappearattheQoutput.Inputscanbedrive

74LVC1G80GS,132

Package：6-XFDFN；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 功能：標(biāo)準(zhǔn) 類別：集成電路（IC） 觸發(fā)器 描述：IC FF D-TYPE SNGL 1BIT 6XSON

74LVC1G80GV

SingleD-typeflip-flop;positive-edgetrigger

DESCRIPTION The74LVC1G80isahigh-performance,low-power,low-voltage,Si-gateCMOSdevice,superiortomostadvancedCMOScompatibleTTLfamilies. Inputscanbedrivenfromeither3.3Vor5Vdevices.Thisfeatureallowstheuseofthisdeviceinamixed3.3Vand5Venvironment. F

74LVC1G80GV

SingleD-typeflip-flop;positive-edgetrigger

1.Generaldescription The74LVC1G80isasinglepositive-edgetriggeredD-typeflip-flop.DataattheD-inputthatmeets theset-upandholdtimerequirementsontheLOW-to-HIGHclocktransitionwillbestoredinthe flip-flopanditscomplementwillappearattheQoutput.Inputscanbedrive