ADP7104ACPZ-3.3-R7中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The ADP7104 is a CMOS, low dropout linear regulator that operates from 3.3 V to 20 V and provides up to 500 mA of output current. This high input voltage LDO is ideal for regulation of high performance analog and mixed signal circuits operating from 19 V to 1.22 V rails. Using an advanced proprietary architecture, it provides high power supply rejection, low noise, and achieves excellent line and load transient response with just a small 1 μF ceramic output capacitor.

FEATURES

Input voltage range: 3.3 V to 20 V

Maximum output current: 500 mA

Low noise: 15 μV rms for fixed output versions

PSRR performance of 60 dB at 10 kHz, VOUT = 3.3 V

Reverse current protection

Low dropout voltage: 350 mV at 500 mA

Initial accuracy: ±0.8

Accuracy over line, load, and temperature

?2 to +1, TJ = ?40°C to +125°C

?1.25 to +1, TJ = 0°C to +85°C

Low quiescent current (VIN = 5 V), IGND= 900 μA with 500 mA load

Low shutdown current: <40 μA at VIN = 12 V, stable with small

1 μF ceramic output capacitor

7 fixed output voltage options: 1.5 V, 1.8 V, 2.5 V, 3 V, 3.3 V,

5 V, and 9 V

Adjustable output from 1.22 V to VIN ? VDO

Foldback current limit and thermal overload protection

User programmable precision UVLO/enable

Power-good indicator

8-lead LFCSP and 8-lead SOIC packages

APPLICATIONS

Regulation to noise sensitive applications: ADC, DAC circuits,

precision amplifiers, high frequency oscillators, clocks,

and PLLs

Communications and infrastructure

Medical and healthcare

Industrial and instrumentation