EVAL-AD4080-FMCZ中文資料亞德諾數(shù)據(jù)手冊PDF規(guī)格書

GENERAL DESCRIPTION

The AD4080 is a high-speed, low noise, low distortion, 20-bit, Easy

Drive, successive approximation register (SAR) analog-to-digital

converter (ADC). Maintaining high performance (signal-to-noise and

distortion (SINAD) ratio > 90 dBFS) at signal frequencies in excess

of 1 MHz enables the AD4080 to service a wide variety of precision,

wide bandwidth data acquisition applications. Simplification of the

input anti-alias filter design can be accomplished by applying oversampling

along with the integrated digital filtering and decimation to

reduce noise and lower the output data rate for applications that do

not require the lowest latency of the AD4080.

The AD4080 Easy Drive features reduce both signal chain complexity

and power consumption while enabling greater channel

density and flexibility in companion component selection. The product

input structure was designed to minimize any input dependent

signal currents; therefore, reducing any converter induced settling

artifacts. The continuous acquisition architecture allows settling

across the entire conversion cycle, easing ADC driver settling and

bandwidth requirements as compared to other high-speed data

converters.

The AD4080 includes several elements that simplify data converter

integration: a low drift reference buffer, low dropout (LDO) regulators

to generate ADC core and digital interface supply rails, and a

16K result data first-in first out (FIFO) that can greatly reduce the

load on the digital host. Additionally, critical supply and reference

decoupling capacitors are integrated in the package to ensure

optimum performance, simplify printed circuit board (PCB) layout,

and reduce the overall solution footprint.

FEATURES

? High performance

? Throughput: 40 MSPS, 46.25 ns conversion latency

? INL: ±4 ppm (typical), ±8 ppm (maximum)

? SNR/THD

? 93.6 dB (typical)/?110 dB (typical) at fIN = 1 kHz

? 93.5 dB (typical)/?104 dB (typical) at fIN = 1 MHz

? Noise spectral density: ?167.6 dBFS/Hz

? 20-bit resolution, no missing codes

? Low power

? 79.3 mW typical at 40 MSPS with ?0.5 dBFS sine-wave input

? Easy Drive, fully differential Input

? 6 V p-p differential input range

? Continuous signal acquisition

? Linearized, 5 μA/MSPS input current

? Integrated, low-drift reference buffer and decoupling

? Integrated VCM generation

? Digital features and data interface

? Conversion result FIFO, 16K sample depth

? Digital averaging filter with up to 210 decimation

? SPI configuration

? Configurable data interface

? Single lane, DDR, serial LVDS, 800 MBPS per lane

? Dual lane, DDR, serial LVDS, 400 MBPS per lane

? Single/quad lane SPI data interface

? Package

? 49-ball, 5 mm x 5 mm CSP_BGA, 0.65 mm pitch

? Integrated supply decoupling capacitors

? Operating temperature range: ?40°C to +85°C

APPLICATIONS

? Digital imaging

? Cell analysis

? Spectroscopy

? Automated test equipment

? High speed data acquisition

? Digital control loops, hardware in the loop

? Power quality analysis

? Source measurement units

? Electron and x-ray microscopy

? Radar level measurement

? Nondestructive test

? Predictive maintenance and structural health