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HD74HC75P中文資料瑞薩數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

HD74HC75P
廠商型號(hào)

HD74HC75P

功能描述

Quad. Bistable Latches

文件大小

103.31 Kbytes

頁(yè)面數(shù)量

8 頁(yè)

生產(chǎn)廠商 Renesas Technology Corp
企業(yè)簡(jiǎn)稱

RENESAS瑞薩

中文名稱

瑞薩科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-5-27 23:01:00

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HD74HC75P規(guī)格書(shū)詳情

Description

This latch is ideally suited for use as temporary storage for binary information processing, input/output, and indicator units. Information present at the data (D) input is transferred to the Q output when the latch enable (LE) is high. The Q output will follow the data input as long as the enable remains high. When the enable goes low, the information that was present at the data input at the time the transition occurred is retained at the Q output unit the enable is permitted to go high again.

Features

? High Speed Operation: tpd (D to Q) = 12.5 ns typ (CL = 50 pF)

? High Output Current: Fanout of 10 LSTTL Loads

? Wide Operating Voltage: VCC = 2 to 6 V

? Low Input Current: 1 μA max

? Low Quiescent Supply Current: ICC (static) = 2 μA max (Ta = 25°C)

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