SLG47512V集成電路（IC）的CPLD（復(fù)雜可編程邏輯器件）規(guī)格書PDF中文資料

? Two High Speed General Purpose Analog Comparators

(ACMPxH)

? Integrated Voltage References (Vref)

? Fifteen Combination Function Macrocells

? Three Selectable DFF/LATCH or 2-bit LUTs or Shift

Registers

? One Selectable Programmable Pattern Generator or

2-bit LUT

? Ten Selectable DFF/LATCH or 3-bit LUTs or

Shift Registers

? One Selectable DFF/LATCH or 4-bit LUTs or

Shift Register

? Eight Multi-Function Macrocells

? Seven Selectable DFF/LATCH or 3-bit LUTs + 8-bit

Delay/Counters

? One Selectable DFF/LATCH or 4-bit LUT + 16-bit

Delay/Counter

? Serial Communications

? I2C Protocol Interface

? Programmable Delay with Edge Detector Output

? Deglitch Filter or Edge Detector

? Two Oscillators (OSC)

? 2.048 kHz Oscillator

? 25 MHz Oscillator

? Analog Temperature Sensor

? Power-On Reset (POR) with CRC Check

? Read Back Protection (Read Lock)