SN74LV4T125PWREP中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

廠商型號	SN74LV4T125PWREP
功能描述	SN74LV4T125-EP Single Power Supply Quadruple Buffer Translator GATE With 3- State Output CMOS Logic Level Shifter
絲印標識	L4125EP
封裝外殼	TSSOP
文件大小	1.05524 Mbytes
頁面數(shù)量	23 頁
生產(chǎn)廠商	Texas Instruments
企業(yè)簡稱	TI1【德州儀器】
中文名稱	美國德州儀器公司官網(wǎng)
原廠標識
數(shù)據(jù)手冊	下載地址一下載地址二到原廠下載
更新時間	2025-7-11 10:40:00
人工找貨	SN74LV4T125PWREP價格和庫存，歡迎聯(lián)系客服免費人工找貨

1 Features

? Wide operating range of 1.8V to 5.5V

? Single-supply voltage translator (refer to LVxT

Enhanced Input Voltage):

– Up translation:

? 1.2V to 1.8V

? 1.5V to 2.5V

? 1.8V to 3.3V

? 3.3V to 5.0V

– Down translation:

? 5.0V, 3.3V, 2.5V to 1.8V

? 5.0V, 3.3V to 2.5V

? 5.0V to 3.3V

? 5.5V tolerant input pins

? Supports standard pinouts

? Up to 150Mbps with 5V or 3.3V VCC

? Latch-up performance exceeds 250mA per JESD

2 Applications

? Enable or disable a digital signal

? Controlling an indicator LED

? Translation between communication modules and

system controllers

3 Description

The SN74LV4T125-EP contains four independent

buffers with 3-state outputs and extended voltage

operation to allow for level translation. Each buffer

performs the Boolean function Y = A in positive logic.

The outputs can be put into a high impedance (Hi-Z)

state by applying a HIGH on the OE pin. The output

level is referenced to the supply voltage (VCC) and

supports 1.8V, 2.5V, 3.3V, and 5V CMOS levels.

The input is designed with a lower threshold circuit to

support up translation for lower voltage CMOS inputs

(for example, 1.2V input to 1.8V output or 1.8V input

to 3.3V output). In addition, the 5V tolerant input pins

enable down translation (for example, 3.3V to 2.5V

output).