SN74LVC125APWG4集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器規(guī)格書(shū)PDF中文資料

1 Features

? 3-State outputs

? Separate OE for all 4 buffers

? Operates from 1.65V to 3.6V

? Specified from –40°C to 85°C

and –40°C to 125°C

? Inputs accept voltages to 5.5V

? Max tpd of 4.8ns at 3.3V

? Typical VOLP (output ground bounce)

< 0.8V at VCC = 3.3V, TA = 25°C

? Typical VOHV (output VOH undershoot)

> 2V at VCC = 3.3V, TA = 25°C

? Latch-up performance exceeds 250mA

per JESD 17

2 Applications

? Cable Modem Termination Systems

? IP Phones: Wired and Wireless

? Optical Modules

? Optical Networking:

– EPON or Video Over Fiber

? Point-to-Point Microwave Backhaul

? Power: Telecom DC/DC Modules:

– Analog or Digital

? Private Branch Exchanges (PBX)

? TETRA Base Stations

? Telecom Base Band Units

? Telecom Shelters:

– Filter Units

– Power Distribution Units (PDU)

– Power Monitoring Units (PMU)

– Wireless Battery Monitoring

– Remote Electrical Tilt Units (RET)

– Remote Radio Units (RRU)

– Tower Mounted Amplifiers (TMA)

? Vector Signal Analyzers and Generators

? Video Conferencing: IP-Based HD

? WiMAX and Wireless Infrastructure Equipment

? Wireless Communications Testers

? xDSL Modems and DSLAM

3 Description

This quadruple bus buffer gate is designed for 1.65V

to 3.6V VCC operation.

The SN74LVC125A device features independent line

drivers with 3-state outputs. Each output is disabled

when the associated output-enable (OE) input is high.

To ensure the high-impedance state during power up

or power down, OE should be tied to VCC through

a pullup resistor; the minimum value of the resistor

is determined by the current-sinking capability of the

driver.

Inputs can be driven from either 3.3V or 5V devices.

This feature allows the use of this device as a

translator in a mixed 3.3V/5V system environment.