SN74LVTH16374ZRDR集成電路（IC）的觸發(fā)器規(guī)格書PDF中文資料

SN74LVTH16374ZRDR屬于集成電路（IC）的觸發(fā)器。由美國(guó)德州儀器公司制造生產(chǎn)的SN74LVTH16374ZRDR觸發(fā)器觸發(fā)器是能夠存儲(chǔ)單個(gè)邏輯狀態(tài)或信息“位”的基本數(shù)字存儲(chǔ)器件。這些器件至少有兩個(gè)輸入；一個(gè)或多個(gè)用于傳遞要存儲(chǔ)的數(shù)據(jù)，另一個(gè)用于指示存儲(chǔ)該數(shù)據(jù)的時(shí)間點(diǎn)。不同的觸發(fā)器類型，例如 D（延遲）、SR（置位復(fù)位）和 JK，對(duì)提供給其輸入的信號(hào)有不同的響應(yīng)，可用于實(shí)現(xiàn)不同的邏輯功能。這些器件與鎖存器的不同之處在于它們是邊緣敏感器件，其保持的邏輯狀態(tài)僅在接收到有效時(shí)鐘信號(hào)時(shí)才會(huì)改變。

FEATURES

· Members of the Texas Instruments Widebus?

Family

· State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V Operation

and Low Static-Power Dissipation

· Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V VCC)

· Support Unregulated Battery Operation Down

to 2.7 V

· Typical VOLP (Output Ground Bounce) <0.8 V at

VCC = 3.3 V, TA = 25°C

· Ioff and Power-Up 3-State Support Hot Insertion

· Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

· Distributed VCC and GND Pins Minimize

High-Speed Switching Noise

· Flow-Through Architecture Optimizes PCB

Layout

· Latch-Up Performance Exceeds 500 mA Per

JESD 17

· ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)

– 200-V Machine Model (A115-A)

DESCRIPTION/ORDERING INFORMATION

The 'LVTH16374 devices are 16-bit edge-triggered D-type flip-flops with 3-state outputs designed for low-voltage

(3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. These

devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working

registers.

These devices can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock

(CLK), the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or

low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the

bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines

without need for interface or pullup components.

OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors

with the bus-hold circuitry is not recommended.