STM32WB55XX中文資料意法半導(dǎo)體數(shù)據(jù)手冊(cè)PDF規(guī)格書

Introduction

This document provides the ordering information and mechanical device characteristics of the STM32WB55xx and STM32WB35xx microcontrollers, based on Arm? cores(a).

This document must be read in conjunction with the reference manual (RM0434), available from the STMicroelectronics website www.st.com.

For information on the Arm? Cortex?-M4 and Cortex?-M0+ cores, refer, respectively, to the Cortex?-M4 Technical Reference Manual and to the Cortex?-M0+ Technical Reference Manual, both available on the www.arm.com website.

For information on 802.15.4 refer to the IEEE website (www.ieee.org).

For information on Bluetooth? refer to www.bluetooth.com.

Description

The STM32WB55xx and STM32WB35xx multiprotocol wireless and ultra-low-power devices embed a powerful and ultra-low-power radio compliant with the Bluetooth? Low Energy SIG specification v5.0 and with IEEE 802.15.4-2011. They contain a dedicated Arm? Cortex? -M0+ for performing all the real-time low layer operation.

The devices are designed to be extremely low-power and are based on the highperformance Arm? Cortex?-M4 32-bit RISC core operating at a frequency of up to 64 MHz.

This core features a Floating point unit (FPU) single precision that supports all Arm? single-precision data-processing instructions and data types. It also implements a full set of DSP instructions and a memory protection unit (MPU) that enhances application security.

Enhanced inter-processor communication is provided by the IPCC with six bidirectional channels. The HSEM provides hardware semaphores used to share common resources between the two processors.