首頁(yè)>V62SLASH18602-01XE>規(guī)格書(shū)詳情
V62SLASH18602-01XE中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

廠商型號(hào) |
V62SLASH18602-01XE |
功能描述 | LMK04828-EP Ultra-Low-Noise, JESD204B-Compliant Clock Jitter Cleaner |
文件大小 |
1.76875 Mbytes |
頁(yè)面數(shù)量 |
102 頁(yè) |
生產(chǎn)廠商 | Texas Instruments |
企業(yè)簡(jiǎn)稱(chēng) |
TI【德州儀器】 |
中文名稱(chēng) | 美國(guó)德州儀器公司官網(wǎng) |
原廠標(biāo)識(shí) | ![]() |
數(shù)據(jù)手冊(cè) | |
更新時(shí)間 | 2025-7-14 15:15:00 |
人工找貨 | V62SLASH18602-01XE價(jià)格和庫(kù)存,歡迎聯(lián)系客服免費(fèi)人工找貨 |
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V62SLASH18602-01XE規(guī)格書(shū)詳情
1 Features
1? EP Features
– Gold Bondwires
– Temperature Range: –55 to +105 °C
– Lead Finish SnPb
? Maximum Distribution Frequency: 3.2 GHz
? JESD204B Support
? Ultra-Low RMS Jitter
– 88-fs RMS Jitter (12 kHz to 20 MHz)
– 91-fs RMS Jitter (100 Hz to 20 MHz)
– –162.5 dBc/Hz Noise Floor at 245.76 MHz
? Up to 14 Differential Device Clocks From PLL2
– Up to 7 SYSREF Clocks
– Maximum Clock Output Frequency 3.2 GHz
– LVPECL, LVDS, HSDS, LCPECL
Programmable Outputs From PLL2
? Up to 1 Buffered VCXO/Crystal Output From PLL1
– LVPECL, LVDS, 2xLVCMOS Programmable
? Multi-Mode: Dual PLL, Single PLL, and Clock
Distribution
? Dual Loop PLLatinum? PLL Architecture
? PLL1
– Up to 3 Redundant Input Clocks
– Automatic and Manual Switchover Modes
– Hitless Switching and LOS
– Integrated Low-Noise Crystal Oscillator Circuit
– Holdover Mode When Input Clocks are Lost
? PLL2
– Normalized [1 Hz] PLL Noise Floor of
–227 dBc/Hz
– Phase Detector Rate up to 155 MHz
– OSCin Frequency-Doubler
– Two Integrated Low-Noise VCOs
? 50% Duty Cycle Output Divides, 1 to 32
(Even and Odd)
? Precision Digital Delay, Dynamically Adjustable
? 25-ps Step Analog Delay
? 3.15-V to 3.45-V Operation
? Package: 64-Pin WQFN (9.0 mm × 9.0 mm × 0.8
mm)
2 Applications
? Wireless Infrastructure
? Data Converter Clocking
? Networking, SONET/SDH, DSLAM
? Medical / Video / Military / Aerospace
? Test and Measurement
3 Description
The LMK04828-EP device is the industry's highest
performance clock conditioner with JESD204B
support.
The 14 clock outputs from PLL2 can be configured to
drive seven JESD204B converters or other logic
devices using device and SYSREF clocks. SYSREF
can be provided using both DC and AC coupling. Not
limited to JESD204B applications, each of the 14
outputs can be individually configured as highperformance
outputs for traditional clocking systems.
The high performance combined with features like the
ability to trade off between power or performance,
dual VCOs, dynamic digital delay, holdover, and
glitchless analog delay make the LMK04828-EP ideal
for providing flexible high-performance clocking trees.
供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
---|---|---|---|---|---|---|---|
2023+ |
13000 |
進(jìn)口原裝現(xiàn)貨 |
詢(xún)價(jià) | ||||
22+ |
SOT-223 |
25000 |
只有原裝原裝,支持BOM配單 |
詢(xún)價(jià) | |||
現(xiàn)貨很近!原廠很遠(yuǎn)!只做原裝 |
20+ |
TO-223 |
32500 |
現(xiàn)貨很近!原廠很遠(yuǎn)!只做原裝 |
詢(xún)價(jià) | ||
VANGO |
17+ |
QFN68 |
880000 |
明嘉萊只做原裝正品現(xiàn)貨 |
詢(xún)價(jià) | ||
45 |
公司優(yōu)勢(shì)庫(kù)存 熱賣(mài)中! |
詢(xún)價(jià) | |||||
N/A |
2450+ |
QFN |
6540 |
只做原裝正品假一賠十為客戶做到零風(fēng)險(xiǎn)!! |
詢(xún)價(jià) | ||
08+ |
TO-223 |
10000 |
普通 |
詢(xún)價(jià) | |||
24+ |
SOT5 |
3629 |
原裝優(yōu)勢(shì)!房間現(xiàn)貨!歡迎來(lái)電! |
詢(xún)價(jià) | |||
23+ |
QFN |
84 |
原裝現(xiàn)貨假一賠十 |
詢(xún)價(jià) | |||
17+ |
SOT-223 |
6200 |
100%原裝正品現(xiàn)貨 |
詢(xún)價(jià) |