ZL30256

3-Channel, 10-In/18-Out Jitter Attenuator; Up to 3 independent DPLL channels\nExcellent jitter performance of 180 fs RMS in 12 kHz to 20 MHz band meets jitter requirements of 10G/40G and 100G PHYs\nTwo programmable ultra-low jitter synthesizers generate any frequency from 1 Hz to 1045 MHz\nOne programmable general purpose synthesizer generates any clock from 1Hz to 180 MHz\n8 differential or 16 single ended (CMOS) ultra-low jitter outputs plus two general purpose CMOS outputs\nAccepts up to 10 LVPECL/LVDS/HCSL/LVCMOS inputs\nAny input reference can be fed with clock, sync (frame pulse), clock /sync pair or clock modulated with sync pulse (embedded PPS ePPS and embedded PP2S ePP2S)\nUp to four programmable digital PLLs/NCOs with loop bandwidth from 14 Hz to 470 Hz synchronize to any clock rate from 1 kHz to 900 MHz and to clock plus sync pulse\nAutomatic hitless reference switching and digital holdover on reference fail with initial holdover accuracy better than 1 ppb with post holdover filter\nEasy Configuration and dynamic programming via SPI/I2C interface\nOperates from a single crystal resonator or clock oscillator;

CREATE AND SAMPLE YOUR CUSTOM ZL30256 HEREThe ZL30256 is multi-channel high-performance, any-rate?multiplier and jitter attenuator which simplifies board design by generating ultra-low-jitter clock signals from or attenuating clock signals while generating additional independent frequency families. With 3 independent jitter attenuating DPLL channels, the ability to create 5 different frequency families and best-in-class jitter?performance, the ZL30256 can create complete clock-trees,?improving design reliability, reducing bill of materials (BOM) cost, and simplifying?design by replacing multiple PLLs and peripheral timing components.

ZL30256LFG7

Package：80-VFLGA；包裝：托盤 類別：集成電路（IC） 時鐘發(fā)生器，PLL，頻率合成器 描述：IC JITTER ATTENUATOR 80LGA

ZL30363GDG2

ZARLINK
BGA

ZL30406QGC

ZARLINK
TQFP64

ZL30406QGG1

ZARLINK
QFP64