74HC193DB

Presettable synchronous 4-bit binary up/down counter

Generaldescription The74HC193;74HCT193isa4-bitsynchronousbinaryup/downcounter.Separateup/downclocks,CPUandCPDrespectively,simplifyoperation.TheoutputschangestatesynchronouslywiththeLOW-to-HIGHtransitionofeitherclockinput.IftheCPUclockispulsedwhileCPDishel

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74HC193DB

74HC193DB - Presettable synchronous 4-bit binary up, down counter; ·Input levels:·For 74HC193: CMOS level\n·For 74HCT193: TTL level\n;

Presettable synchronous 4-bit binary up, down counter - The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at any time to guarantee predictable behavior. The device can be cleared at any time by the asynchronous master reset input (MR); it may also be loaded in parallel by activating the asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs can be used as the clock input signals to the next higher order circuit in a multistage counter, since they duplicate the clock waveforms. Multistage counters will not be fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input will disable the parallel load gates, override both clock inputs and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC.

74HC193DB

Presettable synchronous 4-bit binary up/down counter

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74HC193DB-Q100

74HC193DB-Q100 - Presettable synchronous 4-bit binary up/down counter ; ·Automotive product qualification in accordance with AEC-Q100 (Grade 1)·Specified from -40 °C to +85 °C and from -40 °C to +125 °C\n;

Presettable synchronous 4-bit binary up/down counter - The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is pulsed while CPD is held HIGH, the device counts up. If the CPD clock is pulsed while CPU is held HIGH, the device counts down. Only one clock input can be held HIGH at any time to guarantee predictable behavior. The device can be cleared at any time by the asynchronous master reset input (MR). It may also be loaded in parallel by activating the asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count down (TCD) outputs are normally HIGH. When the circuit has reached the maximum count state of 15, the next HIGH-to-LOW transition of CPU causes TCU to go LOW. TCU remains LOW until CPU goes HIGH again, duplicating the count up clock. Likewise, the TCD output goes LOW when the circuit is in the zero state and the CPD goes LOW. The terminal count outputs duplicate the clock waveforms and can be used as the clock input signals to the next higher-order circuit in a multistage counter. Multistage counters are not fully synchronous, since there is a slight delay time difference added for each stage that is added. The counter may be preset by the asynchronous parallel load capability of the circuit. Information on the parallel data inputs (D0 to D3), is loaded into the counter. This information appears on the outputs (Q0 to Q3) regardless of the conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on the master reset (MR) input disables the parallel load gates. It overrides both clock inputs and sets all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a reset or load operation, the next LOW-to-HIGH transition of that clock is interpreted as a legitimate signal and it is counted. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications.

74HC193DB-Q100

Presettable synchronous 4-bit binary up/down counter

74HC193DB,112

Package：16-SSOP（0.209"，5.30mm 寬）；包裝：管件 類別：集成電路（IC） 計數(shù)器，除法器 描述：IC SYNC 4BIT BINARY UP/DN 16SSOP

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74HC193DB,118

Package：16-SSOP（0.209"，5.30mm 寬）；包裝：管件 類別：集成電路（IC） 計數(shù)器，除法器 描述：IC 4BIT BINAR UP/DN COUNT 16SSOP

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74HC193DB-Q100J

Package：16-SSOP（0.209"，5.30mm 寬）；包裝：卷帶（TR）剪切帶（CT）Digi-Reel? 得捷定制卷帶 類別：集成電路（IC） 計數(shù)器，除法器 描述：IC COUNTER U/D 4BIT BIN 16SSOP

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